This invention relates generally to integrated circuits, and more specifically to a method for forming fuse windows and bond pad openings in an integrated circuit.
The semiconductor industries continuing drive toward integrated circuits with ever decreasing geometries coupled with its pervasive use of highly reflective interconnect materials such as polysilicon, aluminum, refractory metals and metal silicides has led to increased photolithography patterning problems. Unwanted reflections from these underlying interconnect materials during the photoresist patterning process cause the interconnect photoresist pattern and the resulting interconnect to be distorted. This problem is further compounded when photolithographic imaging tools having ultraviolet and deep ultraviolet exposure wavelengths are used to generate the photoresist patterns.
One technique proposed to minimize reflections from an underlying reflective interconnect material is to form an anti-reflective coating over it prior to photoresist patterning. However, integration of the anti-reflective coating into the fabrication process has been problematic. For example, it has been found that bond pads formed using a titanium nitride anti-reflective coating have poor adhesion to subsequently formed wire bonds. Therefore, the titanium nitride anti-reflective coating must be removed prior to forming the wire bond to the bonding pad. Removal of this titanium nitride anti-reflective coating, however, adversely affects the formation of fuse windows on other portions of the integrated circuit. More specifically, if fuse windows and bonding pad openings are formed at the same time, then the fuse window is over etched and the underlying fuse is exposed because the titanium nitride anti-reflective coating etches at a much slower rate than does the dielectric layer overlying the fuse. Exposure of the fuse adversely effects the reliability of the integrated circuit because the fuse may corrode if it is exposed, especially if the integrated circuit uses aluminum fuses.
Accordingly a need exists for a method that reliably allows fuse windows and bond pad openings to be formed within integrated circuits.